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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 24a. FIFO Read Channel Tags (TAG[3:0])
CHANNEL TAGS
TAG3
0
0
0
0
0
0
0
1
1
1
1
1
TAG2
0
0
0
0
1
1
1
0
0
0
0
1
TAG1
0
0
1
1
0
0
1
0
0
1
1
1
TAG0
0
1
0
1
0
1
0
0
1
0
1
0
ADC DATA DESCRIPTION
Internal temperature sensor measurement. ADCMON bit must be set.
Channel 1 external temperature measurement. ADCMON bit must be set.
Channel 1 drain current measurement. ADCMON bit must be set.
ADCIN1 input measurement. ADCMON bit must be set.
Channel 2 external temperature measurement. ADCMON bit must be set.
Channel 2 drain current measurement. ADCMON bit must be set.
ADCIN2 input measurement. ADCMON bit must be set.
Channel 1 temperature average. AVGMON bit must be set.
Channel 1 APC average. AVGMON bit must be set.
Channel 2 temperature average. AVGMON bit must be set.
Channel 2 APC average. AVGMON bit must be set.
Error tag. Indicates data may be corrupted.
Empty FIFO tag. This tag appears during a FIFO read if the FIFO is empty at the time the read
1
1
1
1
command is made. In addition to this channel tag, the current value of the Flag register is
provided in place of the ADC data.
Table 25. Software Clear Register
DATA BITS
D[15:7]
BIT NAME
Unused
RESET STATE
X
Unused bits.
FUNCTION
Full reset bit. If ARMRST has been set to 1 in a previous write operation, set
D6
FULLRST
NA
FULLRST to 1 to perform a full reset. Otherwise, a full reset will not be
performed and the value of FULLRST remains unchanged.
D5
D4
D3
D2
D1
D0
ARMRST
ALMSCLR
AVGCLR
FIFOCLR
DAC2RST
DAC1RST
0
NA
NA
NA
NA
NA
Full reset enable bit. Set to 1 at the same time FULLRST is set to 0 to
enable full reset capabilities.
Alarm threshold registers reset bit. Set to 1 to clear all alarm threshold
registers and their respective flags in the Flag register.
Average clear enable bit. Set the AVGCLR bit to 1 to clear the average and
hysteresis memory for all lookup operations.
FIFO clear bit. Set to 1 to clear the FIFO.
DAC 2 reset bit. Set to 1 to clear DAC2 input and output registers.
DAC 1 reset bit. Set to 1 to clear DAC1 input and output registers.
X = Don’t care.
NA = Not applicable.
64
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